1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and the semiconductor device, and more particularly, to a semiconductor device having a contact hole which is capable of maintaining contact resistance of a contact connecting multi-layered interconnections and a method for manufacturing the same.
2. Description of the Related Art
As the integration density of semiconductor devices increases, a multi-layered interconnection structure is required. However, in most cases, an insulating layer on which an interconnection layer will be placed is not flat, and thus contact resistance is not uniform along the entire surface of a semiconductor substrate. This problem will be described with reference to FIG. 1.
Referring to FIG. 1, a transistor (not shown) or a capacitor (not shown) is formed on a semiconductor substrate 10, and a first interlayer insulating layer 12 is formed before an interconnection layer 14 is formed. To planarize the first interlayer insulating layer 12, chemical mechanical polishing (CMP) may be used. Even if the CMP technique is performed on the entire surface of the semiconductor substrate 10, it is very difficult to etch the first interlayer insulating layer 12 to a uniform thickness. In addition, CMP equipment is very expensive.
Thus, in most cases, an interconnection layer 14 and a capping layer 16 are formed on the first interlayer insulating layer 12 that is not planarized. Thus, the thickness of a second interlayer insulating layer 18 formed on the interlayer insulating layer 12 is not uniform.
The interconnection layer 14 is a metal layer containing aluminum. Contact holes 20a, 20b and 20c are formed by etching predetermined portions of the second interlayer insulating layer 18 covering the interconnection layer 14. In this case, oxygen components in the second interlayer insulating layer 18 may diffuse outwardly and then react with aluminum components in the interconnection layer 14 exposed by the contact holes 20a, 20b and 20c. Due to the reaction of oxygen with aluminum, an aluminum oxide layer (not shown), an insulating layer, is formed on the bottom surface of the contact holes 20a, 20b and 20c, that is, the top surface of the interconnection layer 14. To prevent the formation of the aluminum oxide layer, a capping layer 16, which is conductive and can prevent the reaction of oxygen with aluminum is formed on the interconnection layer 14. The capping layer 16 is usually formed of TiN, Ti/TiN, or TaN. Since the capping layer 16 has high resistance, the capping layer 16 is slightly etched to a predetermined depth so that the bottom surface of the contact holes 20a, 20b and 20c is within the capping layer 16.
As described above, the thickness of the second interlayer insulating layer 18 covering the interconnection layer 14 and the capping layer 16 is not uniform along the entire surface of the semiconductor substrate 10. Accordingly, the thickness of the capping layer 16 remaining on the interconnection layer 14 after the etching process for forming the contact holes 20a, 20b, and 20c is not uniform. As a result, the contact resistance of the interconnection layer 14 varies, and thus the speed of information transmission may be different for different regions of the semiconductor device. In other words, the reliability of the semiconductor device may be lowered.